Microdevices are used in myriad ways. Microcircuits, for example, are used in a variety of devices from automobiles to microwaves to personal computers. Other types of microdevices, such as optical devices, photonic structures, mechanical machines or other micro-electromechanical systems (MEMS) and static storage devices show promise to be as important as microcircuit devices are currently. Designing and fabricating microdevices involve many steps. These steps, sometimes referred to as a “design flow,” are highly dependent on the type of microdevice, the complexity, the design team, and the microdevice fabricator or foundry. For microcircuits, several steps are common to all design flows. First, a design specification is modeled logically, typically in a hardware design language (HDL). Software and hardware “tools” then verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are identified and corrected.
After the logical design is satisfactory, it is converted into circuit design data by synthesis software. Preliminary estimates of timing may also be made at this stage using an assumed characteristic speed for each device. The circuit design data, which often takes the form of a listing of circuit components, represents the specific electronic devices, such as transistors, resistors, and capacitors, and their interconnections that will achieve the desired logical result. A simple form of this type of circuit listing is commonly referred to as a “netlist.” A “netlist” typically describes the nodes or “nets” in a circuit, as well as the connection of device pins to those nets. Thus, a netlist can be viewed as corresponding to the level of representation displayed in typical circuit diagrams.
Once the relationships between circuit elements have been established, the design is again transformed, this time into the specific geometric elements that define the shapes that will occur to form the individual elements. Custom layout editors, such as Mentor Graphics' IC Station or Cadence's Virtuoso are commonly used for this task. Automated place and route tools can also be used to define the physical layouts, especially of wires that will be used to interconnect logical elements.
The physical design data represents the patterns that will be written onto the masks used to fabricate the desired microcircuit device, typically by photolithographic processes. Each layer of the integrated circuit has a corresponding layer representation in the physical database, and the geometric shapes described by the data in that layer representation define the relative locations of the circuit elements. For example, the shapes for the layer representation of an implant layer define the regions where doping will occur; the line shapes in the layer representation of an interconnect layer define the locations of the metal wires to connect elements, etc. because the physical design data, also called a “layout”, is used to create the photomasks or reticles used in manufacturing, the data must conform to the requirements of the manufacturing facility, or “fab”, that will manufacture the final devices. Each fab specifies its own physical design parameters for compliance with their process, equipment, and techniques.
It is very important that the physical design information accurately embody the logical design for proper performance. Accordingly, the design flow for a microcircuit will typically include a comparison of the physical layout with the original design schematic. More particularly, the topographical features of the masks are analyzed, to extract the circuit components and the interconnections between the components from the mask layout. The extracted information is arranged into a layout netlist. The extracted layout netlist can then be compared with the original schematic netlist, to ensure that the layout is accurate.
A very large integrated circuit device, however, might have millions and millions of components (for example, transistors) organized into logic gates, memories, programmable field arrays, and other circuits. Comparing two netlists for such a large device might be too consuming to perform on a component by component basis. In order to allow a computer to more easily process these large data structures (and to allow human users to better understand the data structures), the design data for a microcircuit device often is broken up into a hierarchical organization of cells. The six transistors making up one type of memory circuit for storing single bit, for example, may be categorized as a cell. A larger circuit structure containing one or more of these single-bit memory circuits may then be categorized as another cell having a higher hierarchy than the first cell. For example, eight single-bit memory circuits could be categorized as a byte memory circuit cell that includes eight single-bit memory circuit cells.
Thus, rather than having to individually compare each component of a layout circuit listing with its corresponding component in a schematic circuit listing, a layout circuit listing often is compared with a schematic circuit listing using a hierarchical cell (i.e., “h-cell”) comparison process. Using this process, a cell in a schematic circuit listing is compared with its corresponding cell in a layout circuit listing on a component-by-component basis. As used herein, a pair of matching cells is referred to as a “h-cell pair,” and either cell in a an h-cell pair is referred to as an “h-cell.”
Once the accuracy of one instance of an h-cell in the layout circuit listing has been confirmed, the accuracy of the other instances of that h-cell is confirmed without requiring another comparison check. Further, a confirmed h-cell can be treated as a single component of another h-cell having a higher hierarchy. Accordingly, in the example, given above, once the accuracy of one single-bit memory circuit cell serving as an h-cell was confirmed with a component-by-component comparison, the accuracy of all other such single-bit memory circuit h-cells can be confirmed without requiring a transistor-by-transistor comparison. Further, a subsequent component-by-component comparison for a byte memory circuit h-cell would require the comparison of only eight components (that is, a comparison of only the eight single-bit memory circuit cells making up the byte memory circuit h-cell) rather than an individual comparison of all forty-eight transistors forming the byte memory circuit.
While the use of h-cells may allow circuit listings to be compared more efficiently, the difficulty in defining h-cells often present problems. Typically, an h-cell will be defined by a user or by employing a set of heuristics. These heuristics may, for example, look for naming similarities between portions of the layout circuit listing and portions of the schematic circuit listing, similarities in frequency of occurrence between portions of the layout circuit listing and portions of the schematic circuit listing, etc.
As a result, a cell in a layout circuit listing may not have a corresponding cell in a schematic circuit listing required to form an h-cell pair. Thus, with the previously-discussed example, a cell may be defined for the layout circuit listing that includes twelve transistors making up two single-bit memory circuits (i.e., forming a two-bit memory circuit). The schematic listing, however, may only define a cell that includes eighteen transistors making up three single-bit memory circuits (i.e., forming a three-bit memory circuit). With such as arrangement, the cells would not provide an h-cell pair that could be compared, and the circuit listings would still need to be compared on a transistor-by-transistor basis. Further, two different cells having the same or similar names may be designated as equivalents. Comparing this h-cell pair would thus always produce errors. Again, the circuit listings would still need to be compared on a transistor-by-transistor basis.